The claimed invention relates generally to the field of digital circuits, and more particularly but not by way of limitation, to a clock divider circuit which generates a repetitive clock signal and which has error detection and both synchronous and asynchronous reset capabilities.
Clock signals are used throughout digital electronics systems to synchronize events communicated among various system integrated circuits (ICs). A master clock generator typically generates a master clock signal which is at a relatively high frequency. This master clock is divided down to provide various secondary clocks at secondary frequencies less than the master frequency. The secondary clocks are provided to various components throughout the system.
At an individual IC level, a phase locked loop (PLL) circuit is often used to generate internal clocks for use within the IC. The clocks generated by such PLL circuits are typically synchronized to an external master clock or other reference.
Reliable operation of an electronic system depends in large measure on accurate clock signals. However, for a variety of reasons clock dividers can undesirably provide outputs that are orders of magnitude off from the target clock frequency. Heretofore, there has not been a practical way to detect, report and correct such erroneous outputs, especially when the clock signals are generated and used internally within an IC.
Accordingly, there is a need in the art for an improved clock divider circuit with the capability of detecting and resetting an erroneous output condition
In accordance with preferred embodiments, a clock divider circuit is used to generate a divided clock signal from a master clock signal. The clock divider circuit includes a ring counter comprising a ring of serially connected elements clocked by a master clock signal. Each element has a corresponding output state.
During steady-state operation, a different one of the output states is set at a first logical level (such as a logical 1) and each of the remaining output states is set at a second logical level (such as a logical 0) at each successive clock transition in the master clock signal. A gate network uses the respective logical levels of the output states to generate the divided clock signal.
An error detection circuit provides an error detection signal indicative of an error condition when a number of the output states at the first logical level is not equal to one. The error detection circuit further synchronously resets the ring counter so that one of the output states is set at the first logical level and the remaining output states are set at the second logical level in response to the detection of the error condition.
Preferably, the ring counter is further configured to be asynchronously reset by an external processor device in response to the error detection signal. The ring of elements preferably comprises a sequence of serially connected flip-flops each having an input and an output, wherein the output of each flip-flop in the sequence is connected to the input of the next flip-flop in the sequence. The ring counter is preferably characterized as a variable length ring counter so that the total number of available states exceeds the divider value; that is, less than all of the available flip-flops and associated output states can be selected during operation.
The error detection circuit preferably comprises an OR gate configured to perform a logical OR operation upon all of the states except for one, and comprises an AND gate configured to perform a logical AND operation upon the remaining one of said states. The result of the logical AND operation will be high if more than one output state is at the first logical level. The clock divider circuit is preferably embedded in an integrated circuit which further embeds a master clock generator circuit that generates the master clock signal.
These and various other features and advantages that characterize the claimed invention will be apparent upon reading the following detailed description and upon review of the associated drawings.